Samsung’s HBM5 Targets 2× Performance as zHBM Pushes Memory-Compute Integration Further

Samsung is accelerating its next-generation memory roadmap as AI workloads continue to demand higher bandwidth, greater efficiency and more advanced memory architectures.

At SEMICON Taiwan 2026, Samsung outlined new targets for HBM5 and zHBM, while also advancing zNAND-O as another high-performance memory solution. Together, these technologies point to a roadmap that goes beyond simply increasing HBM bandwidth — with greater emphasis on thermal management, power efficiency, memory density and tighter integration between memory and compute.

HBM5: 2× the Performance of HBM4E

Samsung’s HBM5 development is centered on a significant performance increase over HBM4E.

According to reporting from TrendForce and Tom’s Hardware, Samsung is targeting:

2× the performance of HBM4E

20% higher performance per watt

20% lower thermal resistance

The thermal improvement is particularly important as AI accelerators continue to consume more power and generate more heat. Samsung has also previously introduced a Heat Path Block (HPB) approach for HBM5, designed to reduce thermal resistance and simplify cooling.

Samsung is also expected to move the HBM5 base die to a more advanced 2nm process, compared with the 4nm process used for HBM4 and HBM4E, according to reporting cited by TrendForce.

Tom’s Hardware notes that Samsung’s target of doubling HBM4E performance would require a substantial increase in bandwidth. However, the exact HBM5 interface configuration has not been confirmed. Suggestions such as a 4,096-bit interface remain speculative and should not be treated as an official HBM5 specification.

zHBM: Moving Memory Directly Above the Processor

While HBM5 focuses on improving the existing HBM architecture, zHBM represents a more fundamental change in how memory and compute are physically arranged.

Conventional HBM places memory stacks alongside the AI accelerator and connects them through an advanced packaging architecture. Samsung’s zHBM instead places the memory directly above the processor, shortening the physical distance that data needs to travel between memory and compute.

Samsung’s FMS 2026 materials described a next-generation interface system incorporating zHBM as expected to deliver approximately:

8× the performance of HBM5

3× higher energy efficiency

More than 10× the memory density of HBM5

More than 50% lower thermal resistance

These figures come from Samsung’s earlier FMS 2026 announcement. The later SEMICON reporting uses a different comparison baseline for zHBM, describing targets of 8× performance and 3× performance per watt versus HBM4E, with a reported 75–90% reduction in thermal resistance. Because the baselines and reporting contexts differ, the figures should not be combined or treated as a single performance multiplier.

The architectural principle behind zHBM is nevertheless clear: bring memory and compute physically closer together to reduce data-travel distance and improve bandwidth and power efficiency.

zNAND-O: Bringing Higher Performance to NAND

Samsung’s roadmap is not limited to HBM.

The company is also developing zNAND-O, a next-generation NAND solution aimed at combining higher density with improved performance.

According to TrendForce, zNAND-O is targeting:

10× the bit density of DRAM

7× the read bandwidth and power efficiency of NAND

The technology is being developed to address AI workloads that require a combination of high capacity and faster data access, particularly as generative AI and large language models increase memory and storage requirements. TrendForce reports that sampling is targeted for 2028.

Samsung’s CUBE Strategy

These technologies are part of Samsung’s broader CUBE memory strategy:

C - Capacity
Increasing memory capacity through vertical expansion without necessarily increasing the PCB footprint.

U - Utilization
Optimizing 3D memory structures and the placement of logic and memory to improve utilization and reduce latency.

B - Bandwidth
Shortening die-to-die distances and using vertical high-speed connections to increase data movement efficiency.

E - Efficiency
Reducing the energy required to move each bit of data while improving performance per watt.

This framework helps explain why Samsung is developing several different memory architectures rather than relying on a single solution.

From Faster HBM to 3D Memory Integration

Samsung’s roadmap can be viewed as three different approaches to three different memory challenges:

HBM5
→ Increase performance and efficiency within the HBM architecture.

zHBM
→ Move toward direct 3D integration between memory and compute.

zNAND-O
→ Increase the performance of high-density NAND for AI-oriented workloads.

The most notable shift is therefore not simply the move from HBM4E to HBM5. It is Samsung’s longer-term effort to rethink where memory sits, how data moves between memory and compute, and how much power and thermal overhead that movement creates.

For AI systems, memory performance is increasingly tied to the physical architecture of the entire package. Samsung’s roadmap suggests that future gains will come not only from faster interfaces, but also from advanced process technology, 3D integration, thermal design and memory density.

Sources:

TrendForce — “Samsung Unveils Memory Roadmap at SEMICON: HBM5 Targets 2× HBM4E Performance, zHBM 8× Boost,” Sep 1, 2026.

TechPowerUp — “Samsung New Memory Roadmap: HBM5 Aims for 2× Performance, zHBM for 8×,” Sep 2, 2026.